1. Field of the Invention
The present invention relates to a driver circuit, and particularly relates to a driver circuit made up of transistors all being an identical conductive type. Further, the driver circuit according to the present invention also includes a function as a level converting circuit.
2. Description of the Background Art
A driver circuit that drives a capacitive load (load capacitance) is widely known, and for example, a driver circuit made up transistors all being an identical conductive type, namely a driver circuit configured only using transistors of the same conductive type is disclosed in U.S. Pat. No. 3,506,851, Japanese Patent Application Laid-Open No S52-116059, and “Low-Power a-Si Level Shifter for Mobile Displays with Bootstrapped Capacitor and Pulsed Signal Source” (written by Won-Kyu Lee, et al., SID 07 DIGEST, pp. 218-221). The driver circuit made up only of transistors of the same conductive type is advantageous in being capable of seeking simplification of a manufacturing process and reduction in manufacturing cost due to the simplification.
For example, FIG. 2 of U.S. Pat. No. 3,506,851 discloses a driver circuit configured only using p-type MOS transistors. This driver circuit has a bootstrap circuit (bootstrap inverter), made up of three transistors (5, 7, 12) and a capacitive element (C) being a feedback capacitance, as an input stage and a push-pull circuit made up of p-type MOS transistors (17, 18) as an output stage.
The push-pull circuit is made up of the two transistors (17, 18) series-connected between a high-side power source (ground voltage) and a low-side power source (−V), and a connection node therebetween is used as an output terminal of the driver circuit. Namely, out of those two transistors, the one transistor (17) serves to supply the output terminal with a low (L) level voltage (voltage −V), and the other transistor (18) serves to supply the output terminal with a high (H) level voltage (ground voltage).
The two transistors (17, 18) of the push-pull circuit are controlled so as to be mutually complementarily (alternately) turned on, and in a steady state, a direct current (through current from the high-side power source to the low-side power source) does not flow through those two transistors. It is thus possible by the driver circuit having the push-pull circuit as the output stage to seek improvement in driving ability (current driving force) of the driver circuit while seeking reduction in power consumption thereof.
The bootstrap circuit as the input stage of the driver circuit of FIG. 2 of U.S. Pat. No. 3,506,851 drives the above-mentioned one transistor (17) (hereinafter referred to as “transistor 17”). For example, in setting an output signal (OUTPUT) of the driver circuit at an L-level, this bootstrap circuit lowers a gate voltage of the transistor 17 to the low-side power voltage (−V), to turn on the transistor 17. When the transistor 17 is turned on, the output terminal is discharged, to be set at the L-level.
However, since the transistor 17 operates in a saturated region at this time, the L-level voltage of its output signal becomes a voltage (−V+Vth) obtained by superimposing a voltage corresponding to a threshold voltage (Vth) of the transistor 17 on the low-side power voltage (−V). Namely, there is a problem with the driver circuit of FIG. 2 of U.S. Pat. No. 3,506,851 in that a loss corresponding to the threshold voltage of the transistor 17 occurs in the L-level voltage of the output signal.
Further, since a source of the transistor 17 is connected to the output terminal, in discharging the output terminal to be set at the L-level, the transistor 17 performs a source follower operation in the saturated region. Namely, as the output terminal approaches an ultimate L-level voltage (−V+Vth), a gate-source voltage difference of the transistor 17 approaches the threshold voltage (Vth). That is, the more the output terminal approaches the ultimate L-level voltage (−V+Vth), the higher an on-resistance value of the transistor 17 becomes. This causes a decrease in falling speed of the output signal, to hinder an accelerated operation.
A driver circuit of FIG. 3 of U.S. Pat. No. 3,506,851 seeks improvement in the above problem. In this driver circuit, a circuit for an input stage that drives a transistor (26) (hereinafter referred to as “transistor 26”) for setting the output terminal at the L-level is not a bootstrap circuit, but a normal ratio-type inverter (transistors 21, 27), provided that a capacitive element (C) is connected as a feedback capacitance between the output terminal and a gate of the transistor 26, and a delay capacitive element (Cd) for delaying the falling timing of an output signal (OUTPUT) is further connected to the output terminal.
In turning on the transistor 26 to set an output signal (OUTPUT) of the driver circuit at the L-level, the ratio-type inverter does not lower a gate voltage of the transistor 26 to the low-side power voltage (−V). Namely, the ratio-type inverter is only capable of lowering the gate voltage of the transistor 26 to the voltage (−V+Vth) obtained by superimposing a voltage corresponding to a threshold voltage (Vth) of the transistor 26 on the low-side power voltage (−V).
However, immediately thereafter, a voltage change of an output signal that trails down after a delay due to an action of the delay capacitive element (Cd) is transmitted to the gate voltage of the transistor 26 through the feedback capacitance (C), and the gate voltage further falls. As a consequence, the gate voltage of the transistor 26 becomes lower than −V+Vth, the transistor 26 operates in a non-saturated region, and the L-level of the output signal becomes equivalent to the low-side power voltage (−V). Namely, the above-mentioned problem of occurrence of a loss corresponding to the threshold voltage Vth of the transistor in the L-level voltage of the output signal is solved.
Further, since the gate voltage of the transistor 26 is set to a sufficiently low value, even when the output terminal approaches the ultimate L-level voltage (−V), the gate-source voltage can be held large. Accordingly, the problem of the decrease in falling speed of the output signal can be improved as compared with FIG. 2 of U.S. Pat. No. 3,506,851.
It is to be noted that a driver circuit of FIG. 4 of U.S. Pat. No. 3,506,851 functions in a manner similar to the circuit of FIG. 3. In the circuit of FIG. 3, the delay capacitive element (Cd) was provided in the output terminal with an aim to delay the falling timing of the output signal. As opposed to this, in the circuit of FIG. 4, a delay capacitive element is provided in a gate of a transistor (30) for setting the output signal (OUTPUT) at the H-level in order to achieve the same aim as in FIG. 3. Namely, in the circuit of FIG. 4, the falling timing of the output signal is delayed by delaying the timing for turning off the transistor 30 for setting the output signal at the H-level. Since operations other than that are basically the same as those of the circuit of FIG. 3, this circuit also solves the problem of occurrence of a loss in the L-level voltage of the output signal as well as the problem of the decrease in falling speed of the output signal.
As thus described, in the driver circuit shown in FIG. 2 of U.S. Pat. No. 3,506,851 which is made up of the bootstrap circuit and the push-pull circuit, a loss corresponding to the threshold voltage of the transistor 17 occurs in the output-level voltage. Further, the driver circuit also has the problem of the decrease in falling speed of the output signal.
In the circuits of FIGS. 3 and 4 of U.S. Pat. No. 3,506,851, although those problems are improved, there is still room for further improvement in terms of the falling speed of the output signal. For example, in the circuit of FIG. 3, the transistor 26 is driven by the normal ratio-type inverter, but the transistor (27) that sets the gate of the transistor 26 at the L-level for turning on the transistor 26 performs the source follower operation in the saturated region. Hence it is considered that sufficiently lowering the resistance of the transistor 26 requires time, thereby decreasing the falling speed of the output signal.
Further, the output terminal is connected with the delay capacitive element (Cd) for delaying the falling timing of the output signal, and it is considered that charging the element requires time depending upon its capacitance value, thereby decreasing the falling speed of the output signal. In this case, the operation of feeding back the voltage change of the output signal to the gate voltage of the transistor 26 through the delay capacitive element (Cd) also becomes slow, leading to reduction in effect of the improvement in falling speed of the output signal.